tiny.choir.backends.aarch64.encoding
Defined in backends.aarch64.
API (118)
Actions
Public operations.
AddSubImmediate.addAddSubImmediate.addsAddSubImmediate.cmpImmAddSubImmediate.subAddSubImmediate.subsAddSubShiftedRegister.addRegAddSubShiftedRegister.addsRegAddSubShiftedRegister.cmpRegAddSubShiftedRegister.subRegAddSubShiftedRegister.subsRegCondition.invertConditionalBranch.bCondConditionalSelect.cselConditionalSelect.csetDataProcessing2Source.sdivDataProcessing2Source.udivDataProcessing3Source.maddDataProcessing3Source.msubDataProcessing3Source.mulFMovGeneral.fmovFromFprDoubleFMovGeneral.fmovFromFprSingleFMovGeneral.fmovToFprDoubleFMovGeneral.fmovToFprSingleFP1Source.fabsFP1Source.fmovFP1Source.fnegFP1Source.fsqrtFP2Source.faddFP2Source.fdivFP2Source.fmulFP2Source.fsubFPCompare.fcmpFPCompare.fcmpZeroFPImmediate.encodeF32FPImmediate.encodeF64FPImmediate.fmovImmInstruction.fromBytesInstruction.toBytesInstruction.writeLoadStorePair.ldpLoadStorePair.ldpBytesLoadStorePair.ldpPostLoadStorePair.ldpPostBytesLoadStorePair.stpLoadStorePair.stpBytesLoadStorePair.stpPreLoadStorePair.stpPreBytesLoadStorePairFP.ldpLoadStorePairFP.ldpBytesLoadStorePairFP.ldpPostLoadStorePairFP.ldpPostBytesLoadStorePairFP.stpLoadStorePairFP.stpBytesLoadStorePairFP.stpPreLoadStorePairFP.stpPreBytesLoadStoreRegImm.ldrLoadStoreRegImm.strLoadStoreRegImmFP.ldrLoadStoreRegImmFP.strLogicalShiftedRegister.andRegLogicalShiftedRegister.eorRegLogicalShiftedRegister.movRegLogicalShiftedRegister.orrRegMoveWide.movkMoveWide.movnMoveWide.movzUnconditionalBranchImm.bUnconditionalBranchImm.blUnconditionalBranchReg.blrUnconditionalBranchReg.brUnconditionalBranchReg.retUnconditionalBranchReg.retLr
Types and contracts
Public types and contracts.
AddSubExtendAddSubExtendedRegisterAddSubImmediateAddSubImmediate.AddSubOpAddSubShiftAddSubShiftedRegisterBranchConditionConditionalBranchConditionalSelectDataProcessing2SourceDataProcessing2SourceOpcodeDataProcessing3SourceDataProcessingImmediateDataProcessingRegisterFMovGeneralFP1SourceFP1SourceOpcodeFP2SourceFP2Source.FPTypeFP2SourceOpcodeFPCompareFPConversionFPDataProcessingFPImmediateFPImmediateTypeInstructionLoadStoreLoadStoreFPSizeLoadStorePairLoadStorePairFPLoadStorePairFPSizeLoadStorePairModeLoadStoreRegImmLoadStoreRegImmFPLogicalImmediateLogicalOpcodeLogicalShiftLogicalShiftedRegisterMoveWideMoveWideOpcodeUnconditionalBranchImmUnconditionalBranchReg
Values and defaults
Public values and defaults.
Source
Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:32
pub const AddSubExtend = enum(u3) { uxtb = 0b000, uxth = 0b001, uxtw = 0b010, uxtx = 0b011, sxtb = 0b100, sxth = 0b101, sxtw = 0b110, sxtx = 0b111,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:368
pub const AddSubExtendedRegister = packed struct(u32) { rd: Encoded, rn: Encoded, imm3: u3, option: AddSubExtend, rm: Encoded, fixed0: u1 = 1, fixed1: u2 = 0b01, fixed2: u5 = 0b01011, s: u1, op: u1, sf: u1,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:130
pub const AddSubImmediate = packed struct(u32) { rd: Encoded, rn: Encoded, imm12: u12, sh: u1, fixed: u6 = 0b100010, s: u1, op: AddSubOp, sf: u1, pub const AddSubOp = enum(u1) { add = 0, sub = 1 }; pub fn add(rd: Encoded, rn: Encoded, imm: u12, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .add_sub_imm = .{ .rd = rd, .rn = rn, .imm12 = imm, .sh = 0, .s = 0, .op = .add, .sf = @backingInt(size), }, }, }; } pub fn adds(rd: Encoded, rn: Encoded, imm: u12, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .add_sub_imm = .{ .rd = rd, .rn = rn, .imm12 = imm, .sh = 0, .s = 1, .op = .add, .sf = @backingInt(size), }, }, }; } pub fn sub(rd: Encoded, rn: Encoded, imm: u12, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .add_sub_imm = .{ .rd = rd, .rn = rn, .imm12 = imm, .sh = 0, .s = 0, .op = .sub, .sf = @backingInt(size), }, }, }; } pub fn subs(rd: Encoded, rn: Encoded, imm: u12, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .add_sub_imm = .{ .rd = rd, .rn = rn, .imm12 = imm, .sh = 0, .s = 1, .op = .sub, .sf = @backingInt(size), }, }, }; } pub fn cmpImm(rn: Encoded, imm: u12, size: GPRSize) Instruction { return subs(registers.ZR.encoded, rn, imm, size); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:25
pub const AddSubShift = enum(u2) { lsl = 0b00, lsr = 0b01, asr = 0b10, reserved = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:283
pub const AddSubShiftedRegister = packed struct(u32) { rd: Encoded, rn: Encoded, imm6: u6, rm: Encoded, fixed0: u1 = 0, shift: AddSubShift, fixed1: u5 = 0b01011, s: u1, op: u1, sf: u1, pub fn addReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .add_sub_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .shift = .lsl, .s = 0, .op = 0, .sf = @backingInt(size), }, }, }; } pub fn addsReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .add_sub_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .shift = .lsl, .s = 1, .op = 0, .sf = @backingInt(size), }, }, }; } pub fn subReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .add_sub_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .shift = .lsl, .s = 0, .op = 1, .sf = @backingInt(size), }, }, }; } pub fn subsReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .add_sub_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .shift = .lsl, .s = 1, .op = 1, .sf = @backingInt(size), }, }, }; } pub fn cmpReg(rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return subsReg(registers.ZR.encoded, rn, rm, size); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:950
pub const Branch = packed union { unconditional_imm: UnconditionalBranchImm, conditional: ConditionalBranch, unconditional_reg: UnconditionalBranchReg, raw: u32,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1394
pub const Condition = enum(u4) { eq = 0b0000, ne = 0b0001, cs = 0b0010, cc = 0b0011, mi = 0b0100, pl = 0b0101, vs = 0b0110, vc = 0b0111, hi = 0b1000, ls = 0b1001, ge = 0b1010, lt = 0b1011, gt = 0b1100, le = 0b1101, al = 0b1110, nv = 0b1111, pub const hs = Condition.cs; pub const lo = Condition.cc; pub fn invert(self: Condition) Condition { return @fromBackingInt(@intCast(@backingInt(self) ^ 1)); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:985
pub const ConditionalBranch = packed struct(u32) { cond: Condition, fixed0: u1 = 0, imm19: i19, fixed1: u1 = 0, fixed2: u7 = 0b0101010, pub fn bCond(cond: Condition, offset: i19) Instruction { return .{ .branch = .{ .conditional = .{ .cond = cond, .imm19 = offset, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:538
pub const ConditionalSelect = packed struct(u32) { rd: Encoded, rn: Encoded, op2: u2, cond: Condition, rm: Encoded, fixed0: u1 = 0, fixed1: u2 = 0b10, fixed2: u5 = 0b11010, s: u1 = 0, op: u1, sf: u1, pub fn csel(rd: Encoded, rn: Encoded, rm: Encoded, cond: Condition, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .conditional_select = .{ .rd = rd, .rn = rn, .op2 = 0b00, .cond = cond, .rm = rm, .op = 0, .sf = @backingInt(size), }, }, }; } pub fn cset(rd: Encoded, cond: Condition, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .conditional_select = .{ .rd = rd, .rn = registers.ZR.encoded, .op2 = 0b01, .cond = cond.invert(), .rm = registers.ZR.encoded, .op = 0, .sf = @backingInt(size), }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:449
pub const DataProcessing2Source = packed struct(u32) { rd: Encoded, rn: Encoded, opcode: DataProcessing2SourceOpcode, rm: Encoded, fixed: u8 = 0b11010110, s: u1 = 0, fixed2: u1 = 0, sf: u1, pub fn udiv(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .data_proc_2src = .{ .rd = rd, .rn = rn, .opcode = .udiv, .rm = rm, .sf = @backingInt(size), }, }, }; } pub fn sdiv(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .data_proc_2src = .{ .rd = rd, .rn = rn, .opcode = .sdiv, .rm = rm, .sf = @backingInt(size), }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:50
pub const DataProcessing2SourceOpcode = enum(u6) { udiv = 0b000010, sdiv = 0b000011, lslv = 0b001000, lsrv = 0b001001, asrv = 0b001010, rorv = 0b001011,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:488
pub const DataProcessing3Source = packed struct(u32) { rd: Encoded, rn: Encoded, ra: Encoded, o0: u1, rm: Encoded, op31: u3, fixed: u5 = 0b11011, op54: u2, sf: u1, pub fn mul(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return madd(rd, rn, rm, registers.ZR.encoded, size); } pub fn madd(rd: Encoded, rn: Encoded, rm: Encoded, ra: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .data_proc_3src = .{ .rd = rd, .rn = rn, .ra = ra, .o0 = 0, .rm = rm, .op31 = 0b000, .op54 = 0b00, .sf = @backingInt(size), }, }, }; } pub fn msub(rd: Encoded, rn: Encoded, rm: Encoded, ra: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .data_proc_3src = .{ .rd = rd, .rn = rn, .ra = ra, .o0 = 1, .rm = rm, .op31 = 0b000, .op54 = 0b00, .sf = @backingInt(size), }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:123
pub const DataProcessingImmediate = packed union { add_sub_imm: AddSubImmediate, move_wide: MoveWide, logical_imm: LogicalImmediate, raw: u32,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:273
pub const DataProcessingRegister = packed union { add_sub_shifted: AddSubShiftedRegister, add_sub_extended: AddSubExtendedRegister, logical_shifted: LogicalShiftedRegister, data_proc_2src: DataProcessing2Source, data_proc_3src: DataProcessing3Source, conditional_select: ConditionalSelect, raw: u32,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1320
pub const FMovGeneral = packed struct(u32) { rd: Encoded, rn: Encoded, fixed0: u6 = 0b000000, opcode: u3, rmode: u2, fixed1: u1 = 1, ptype: u2, fixed2: u5 = 0b11110, s: u1 = 0, fixed3: u1 = 0, sf: u1, pub fn fmovToFprSingle(rd: Encoded, rn: Encoded) Instruction { return .{ .fp_data_processing = .{ .fmov_general = .{ .rd = rd, .rn = rn, .opcode = 0b111, .rmode = 0b00, .ptype = 0b00, .sf = 0, }, }, }; } pub fn fmovToFprDouble(rd: Encoded, rn: Encoded) Instruction { return .{ .fp_data_processing = .{ .fmov_general = .{ .rd = rd, .rn = rn, .opcode = 0b111, .rmode = 0b00, .ptype = 0b01, .sf = 1, }, }, }; } pub fn fmovFromFprSingle(rd: Encoded, rn: Encoded) Instruction { return .{ .fp_data_processing = .{ .fmov_general = .{ .rd = rd, .rn = rn, .opcode = 0b110, .rmode = 0b00, .ptype = 0b00, .sf = 0, }, }, }; } pub fn fmovFromFprDouble(rd: Encoded, rn: Encoded) Instruction { return .{ .fp_data_processing = .{ .fmov_general = .{ .rd = rd, .rn = rn, .opcode = 0b110, .rmode = 0b00, .ptype = 0b01, .sf = 1, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1063
pub const FP1Source = packed struct(u32) { rd: Encoded, rn: Encoded, fixed0: u5 = 0b10000, opcode: FP1SourceOpcode, fixed1: u1 = 1, ptype: FP2Source.FPType, fixed2: u5 = 0b11110, s: u1 = 0, fixed3: u1 = 0, m: u1 = 0, pub fn fabs(rd: Encoded, rn: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_1src = .{ .rd = rd, .rn = rn, .opcode = .fabs, .ptype = ftype, }, }, }; } pub fn fneg(rd: Encoded, rn: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_1src = .{ .rd = rd, .rn = rn, .opcode = .fneg, .ptype = ftype, }, }, }; } pub fn fsqrt(rd: Encoded, rn: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_1src = .{ .rd = rd, .rn = rn, .opcode = .fsqrt, .ptype = ftype, }, }, }; } pub fn fmov(rd: Encoded, rn: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_1src = .{ .rd = rd, .rn = rn, .opcode = .fmov, .ptype = ftype, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:76
pub const FP1SourceOpcode = enum(u6) { fmov = 0b000000, fabs = 0b000001, fneg = 0b000010, fsqrt = 0b000011,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1128
pub const FP2Source = packed struct(u32) { rd: Encoded, rn: Encoded, fixed0: u2 = 0b10, opcode: FP2SourceOpcode, rm: Encoded, fixed1: u1 = 1, ptype: FPType, fixed2: u5 = 0b11110, m: u1 = 0, fixed3: u1 = 0, s: u1 = 0, pub const FPType = enum(u2) { single = 0b00, double = 0b01, half = 0b11, }; pub fn fadd(rd: Encoded, rn: Encoded, rm: Encoded, ftype: FPType) Instruction { return .{ .fp_data_processing = .{ .fp_2src = .{ .rd = rd, .rn = rn, .opcode = .fadd, .rm = rm, .ptype = ftype, }, }, }; } pub fn fsub(rd: Encoded, rn: Encoded, rm: Encoded, ftype: FPType) Instruction { return .{ .fp_data_processing = .{ .fp_2src = .{ .rd = rd, .rn = rn, .opcode = .fsub, .rm = rm, .ptype = ftype, }, }, }; } pub fn fmul(rd: Encoded, rn: Encoded, rm: Encoded, ftype: FPType) Instruction { return .{ .fp_data_processing = .{ .fp_2src = .{ .rd = rd, .rn = rn, .opcode = .fmul, .rm = rm, .ptype = ftype, }, }, }; } pub fn fdiv(rd: Encoded, rn: Encoded, rm: Encoded, ftype: FPType) Instruction { return .{ .fp_data_processing = .{ .fp_2src = .{ .rd = rd, .rn = rn, .opcode = .fdiv, .rm = rm, .ptype = ftype, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:83
pub const FP2SourceOpcode = enum(u4) { fmul = 0b0000, fdiv = 0b0001, fadd = 0b0010, fsub = 0b0011, fmax = 0b0100, fmin = 0b0101,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1204
pub const FPCompare = packed struct(u32) { opcode2: u5, rn: Encoded, fixed0: u4 = 0b1000, op: u2, rm: Encoded, fixed1: u1 = 1, ptype: FP2Source.FPType, fixed2: u5 = 0b11110, m: u1 = 0, fixed3: u1 = 0, s: u1 = 0, pub fn fcmp(rn: Encoded, rm: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_compare = .{ .opcode2 = 0b00000, .rn = rn, .op = 0b00, .rm = rm, .ptype = ftype, }, }, }; } pub fn fcmpZero(rn: Encoded, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_compare = .{ .opcode2 = 0b01000, .rn = rn, .op = 0b00, .rm = @fromBackingInt(@intCast(0)), .ptype = ftype, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1246
pub const FPConversion = packed struct(u32) { rd: Encoded, rn: Encoded, fixed0: u6 = 0b000000, opcode: u3, rmode: u2, fixed1: u1 = 0, ptype: u2, fixed2: u5 = 0b11110, s: u1 = 0, fixed3: u1 = 0, sf: u1,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1053
pub const FPDataProcessing = packed union { fp_1src: FP1Source, fp_2src: FP2Source, fp_compare: FPCompare, fp_conversion: FPConversion, fp_imm: FPImmediate, fmov_general: FMovGeneral, raw: u32,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1260
pub const FPImmediate = packed struct(u32) { rd: Encoded, fixed0: u5 = 0b00000, fixed1: u3 = 0b100, imm8: u8, ptype: FPImmediateType, fixed2: u5 = 0b11100, fixed3: u4 = 0b0001, fn immTypeFromFP(ftype: FP2Source.FPType) FPImmediateType { return switch (ftype) { .half => .half, .single => .single, .double => .double, }; } pub fn fmovImm(rd: Encoded, imm8: u8, ftype: FP2Source.FPType) Instruction { return .{ .fp_data_processing = .{ .fp_imm = .{ .rd = rd, .imm8 = imm8, .ptype = immTypeFromFP(ftype), }, }, }; } pub fn encodeF32(value: f32) ?u8 { const bits: u32 = @bitCast(value); const sign: u8 = @intCast(bits >> 31); const exp: u8 = @intCast((bits >> 23) & 0xFF); const frac: u32 = bits & 0x7FFFFF; const exp_high: u8 = exp >> 3; if (exp_high != 0x0F and exp_high != 0x10) return null; if ((frac & 0x7FFFF) != 0) return null; const exp_low: u8 = exp & 0x7; const frac_top: u8 = @intCast(frac >> 19); return (sign << 7) | (exp_low << 4) | frac_top; } pub fn encodeF64(value: f64) ?u8 { const bits: u64 = @bitCast(value); const sign: u8 = @intCast(bits >> 63); const exp: u16 = @intCast((bits >> 52) & 0x7FF); const frac: u64 = bits & 0xFFFFFFFFFFFFF; const exp_high: u16 = exp >> 3; if (exp_high != 0x7F and exp_high != 0x80) return null; if ((frac & 0xFFFFFFFFFFFF) != 0) return null; const exp_low: u8 = @intCast(exp & 0x7); const frac_top: u8 = @intCast(frac >> 48); return (sign << 7) | (exp_low << 4) | frac_top; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:92
pub const FPImmediateType = enum(u2) { half = 0b00, single = 0b01, double = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:98
pub const Instruction = packed union { data_processing_imm: DataProcessingImmediate, data_processing_reg: DataProcessingRegister, load_store: LoadStore, branch: Branch, fp_data_processing: FPDataProcessing, raw: u32, pub const size = 4; pub fn toBytes(self: Instruction) [4]u8 { var buf: [4]u8 = undefined; std.mem.writeInt(u32, buf[0..4], self.raw, .little); return buf; } pub fn fromBytes(bytes: [4]u8) Instruction { return .{ .raw = std.mem.readInt(u32, bytes[0..4], .little) }; } pub fn write(self: Instruction, buf: []u8) void { std.mem.writeInt(u32, buf[0..4], self.raw, .little); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:584
pub const LoadStore = packed union { load_store_reg_imm: LoadStoreRegImm, load_store_reg_imm_fp: LoadStoreRegImmFP, load_store_pair: LoadStorePair, load_store_pair_fp: LoadStorePairFP, raw: u32,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:59
pub const LoadStoreFPSize = enum(u2) { single = 0b10, double = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:682
pub const LoadStorePair = packed struct(u32) { rt: Encoded, rn: Encoded, rt2: Encoded, imm7: i7, l: u1, op2: LoadStorePairMode, v: u1 = 0, fixed: u3 = 0b101, opc: u2, pub fn stp(rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_pair = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 0, .op2 = .signed_offset, .opc = @as(u2, @backingInt(gpr_size)) << 1, }, }, }; } pub fn stpBytes(rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, gpr_size: GPRSize) Instruction { const scale: i32 = switch (gpr_size) { .w => 4, .x => 8, }; return stp(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), gpr_size); } pub fn stpPre(rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_pair = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 0, .op2 = .pre_index, .opc = @as(u2, @backingInt(gpr_size)) << 1, }, }, }; } pub fn stpPreBytes(rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, gpr_size: GPRSize) Instruction { const scale: i32 = switch (gpr_size) { .w => 4, .x => 8, }; return stpPre(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), gpr_size); } pub fn ldp(rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_pair = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 1, .op2 = .signed_offset, .opc = @as(u2, @backingInt(gpr_size)) << 1, }, }, }; } pub fn ldpBytes(rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, gpr_size: GPRSize) Instruction { const scale: i32 = switch (gpr_size) { .w => 4, .x => 8, }; return ldp(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), gpr_size); } pub fn ldpPost(rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_pair = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 1, .op2 = .post_index, .opc = @as(u2, @backingInt(gpr_size)) << 1, }, }, }; } pub fn ldpPostBytes(rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, gpr_size: GPRSize) Instruction { const scale: i32 = switch (gpr_size) { .w => 4, .x => 8, }; return ldpPost(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), gpr_size); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:790
pub const LoadStorePairFP = packed struct(u32) { rt: Encoded, rn: Encoded, rt2: Encoded, imm7: i7, l: u1, op2: LoadStorePairMode, v: u1 = 1, fixed: u3 = 0b101, opc: LoadStorePairFPSize, pub fn stp( rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, size: LoadStorePairFPSize, ) Instruction { return .{ .load_store = .{ .load_store_pair_fp = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 0, .op2 = .signed_offset, .opc = size, }, }, }; } pub fn stpBytes( rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, size: LoadStorePairFPSize, ) Instruction { const scale: i32 = switch (size) { .single => 4, .double => 8, .quad => 16, }; return stp(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), size); } pub fn stpPre( rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, size: LoadStorePairFPSize, ) Instruction { return .{ .load_store = .{ .load_store_pair_fp = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 0, .op2 = .pre_index, .opc = size, }, }, }; } pub fn stpPreBytes( rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, size: LoadStorePairFPSize, ) Instruction { const scale: i32 = switch (size) { .single => 4, .double => 8, .quad => 16, }; return stpPre(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), size); } pub fn ldp( rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, size: LoadStorePairFPSize, ) Instruction { return .{ .load_store = .{ .load_store_pair_fp = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 1, .op2 = .signed_offset, .opc = size, }, }, }; } pub fn ldpBytes( rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, size: LoadStorePairFPSize, ) Instruction { const scale: i32 = switch (size) { .single => 4, .double => 8, .quad => 16, }; return ldp(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), size); } pub fn ldpPost( rt: Encoded, rt2: Encoded, rn: Encoded, offset: i7, size: LoadStorePairFPSize, ) Instruction { return .{ .load_store = .{ .load_store_pair_fp = .{ .rt = rt, .rn = rn, .rt2 = rt2, .imm7 = offset, .l = 1, .op2 = .post_index, .opc = size, }, }, }; } pub fn ldpPostBytes( rt: Encoded, rt2: Encoded, rn: Encoded, byte_offset: i32, size: LoadStorePairFPSize, ) Instruction { const scale: i32 = switch (size) { .single => 4, .double => 8, .quad => 16, }; return ldpPost(rt, rt2, rn, scalePairOffsetBytes(byte_offset, scale), size); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:70
pub const LoadStorePairFPSize = enum(u2) { single = 0b00, double = 0b01, quad = 0b10,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:64
pub const LoadStorePairMode = enum(u3) { post_index = 0b001, signed_offset = 0b010, pre_index = 0b011,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:592
pub const LoadStoreRegImm = packed struct(u32) { rt: Encoded, rn: Encoded, imm12: u12, opc: u2, fixed_01: u2 = 0b01, v: u1 = 0, fixed_111: u3 = 0b111, size: u2, pub fn ldr(rt: Encoded, rn: Encoded, offset: u12, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_reg_imm = .{ .rt = rt, .rn = rn, .imm12 = offset, .opc = 0b01, .size = switch (gpr_size) { .w => 0b10, .x => 0b11, }, }, }, }; } pub fn str(rt: Encoded, rn: Encoded, offset: u12, gpr_size: GPRSize) Instruction { return .{ .load_store = .{ .load_store_reg_imm = .{ .rt = rt, .rn = rn, .imm12 = offset, .opc = 0b00, .size = switch (gpr_size) { .w => 0b10, .x => 0b11, }, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:637
pub const LoadStoreRegImmFP = packed struct(u32) { rt: Encoded, rn: Encoded, imm12: u12, opc: u2, fixed_01: u2 = 0b01, v: u1 = 1, fixed_111: u3 = 0b111, size: u2, pub fn ldr(rt: Encoded, rn: Encoded, offset: u12, fp_size: LoadStoreFPSize) Instruction { return .{ .load_store = .{ .load_store_reg_imm_fp = .{ .rt = rt, .rn = rn, .imm12 = offset, .opc = 0b01, .size = @backingInt(fp_size), }, }, }; } pub fn str(rt: Encoded, rn: Encoded, offset: u12, fp_size: LoadStoreFPSize) Instruction { return .{ .load_store = .{ .load_store_reg_imm_fp = .{ .rt = rt, .rn = rn, .imm12 = offset, .opc = 0b00, .size = @backingInt(fp_size), }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:262
pub const LogicalImmediate = packed struct(u32) { rd: Encoded, rn: Encoded, imms: u6, immr: u6, n: u1, fixed: u6 = 0b100100, opc: LogicalOpcode, sf: u1,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:18
pub const LogicalOpcode = enum(u2) { @"and" = 0b00, orr = 0b01, eor = 0b10, ands = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:43
pub const LogicalShift = enum(u2) { lsl = 0b00, lsr = 0b01, asr = 0b10, ror = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:382
pub const LogicalShiftedRegister = packed struct(u32) { rd: Encoded, rn: Encoded, imm6: u6, rm: Encoded, n: u1, shift: LogicalShift, fixed: u5 = 0b01010, opc: LogicalOpcode, sf: u1, pub fn andReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .logical_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .n = 0, .shift = .lsl, .opc = .@"and", .sf = @backingInt(size), }, }, }; } pub fn orrReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .logical_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .n = 0, .shift = .lsl, .opc = .orr, .sf = @backingInt(size), }, }, }; } pub fn eorReg(rd: Encoded, rn: Encoded, rm: Encoded, size: GPRSize) Instruction { return .{ .data_processing_reg = .{ .logical_shifted = .{ .rd = rd, .rn = rn, .imm6 = 0, .rm = rm, .n = 0, .shift = .lsl, .opc = .eor, .sf = @backingInt(size), }, }, }; } pub fn movReg(rd: Encoded, rm: Encoded, size: GPRSize) Instruction { return orrReg(rd, registers.ZR.encoded, rm, size); }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:211
pub const MoveWide = packed struct(u32) { rd: Encoded, imm16: u16, hw: u2, fixed: u6 = 0b100101, opc: MoveWideOpcode, sf: u1, pub fn movz(rd: Encoded, imm: u16, shift: u2, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .move_wide = .{ .rd = rd, .imm16 = imm, .hw = shift, .opc = .movz, .sf = @backingInt(size), }, }, }; } pub fn movk(rd: Encoded, imm: u16, shift: u2, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .move_wide = .{ .rd = rd, .imm16 = imm, .hw = shift, .opc = .movk, .sf = @backingInt(size), }, }, }; } pub fn movn(rd: Encoded, imm: u16, shift: u2, size: GPRSize) Instruction { return .{ .data_processing_imm = .{ .move_wide = .{ .rd = rd, .imm16 = imm, .hw = shift, .opc = .movn, .sf = @backingInt(size), }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:12
pub const MoveWideOpcode = enum(u2) { movn = 0b00, movz = 0b10, movk = 0b11,};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:957
pub const UnconditionalBranchImm = packed struct(u32) { imm26: i26, fixed: u5 = 0b00101, op: u1, pub fn b(offset: i26) Instruction { return .{ .branch = .{ .unconditional_imm = .{ .imm26 = offset, .op = 0, }, }, }; } pub fn bl(offset: i26) Instruction { return .{ .branch = .{ .unconditional_imm = .{ .imm26 = offset, .op = 1, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/instruction.zig:1004
pub const UnconditionalBranchReg = packed struct(u32) { fixed0: u5 = 0b00000, rn: Encoded, fixed1: u6 = 0b000000, op2: u5, opc: u4, fixed2: u7 = 0b1101011, pub fn ret(rn: Encoded) Instruction { return .{ .branch = .{ .unconditional_reg = .{ .rn = rn, .op2 = 0b11111, .opc = 0b0010, }, }, }; } pub fn retLr() Instruction { return ret(GPR.lr.encode()); } pub fn br(rn: Encoded) Instruction { return .{ .branch = .{ .unconditional_reg = .{ .rn = rn, .op2 = 0b11111, .opc = 0b0000, }, }, }; } pub fn blr(rn: Encoded) Instruction { return .{ .branch = .{ .unconditional_reg = .{ .rn = rn, .op2 = 0b11111, .opc = 0b0001, }, }, }; }};Source: lib/choir/src/backends/aarch64/encoding/root.zig
const instruction = @import("instruction.zig");pub const MoveWideOpcode = instruction.MoveWideOpcode;pub const LogicalOpcode = instruction.LogicalOpcode;pub const AddSubShift = instruction.AddSubShift;pub const AddSubExtend = instruction.AddSubExtend;pub const LogicalShift = instruction.LogicalShift;pub const DataProcessing2SourceOpcode = instruction.DataProcessing2SourceOpcode;pub const LoadStoreFPSize = instruction.LoadStoreFPSize;pub const LoadStorePairMode = instruction.LoadStorePairMode;pub const LoadStorePairFPSize = instruction.LoadStorePairFPSize;pub const FP1SourceOpcode = instruction.FP1SourceOpcode;pub const FP2SourceOpcode = instruction.FP2SourceOpcode;pub const FPImmediateType = instruction.FPImmediateType;pub const Instruction = instruction.Instruction;pub const DataProcessingImmediate = instruction.DataProcessingImmediate;pub const AddSubImmediate = instruction.AddSubImmediate;pub const MoveWide = instruction.MoveWide;pub const LogicalImmediate = instruction.LogicalImmediate;pub const DataProcessingRegister = instruction.DataProcessingRegister;pub const AddSubShiftedRegister = instruction.AddSubShiftedRegister;pub const AddSubExtendedRegister = instruction.AddSubExtendedRegister;pub const LogicalShiftedRegister = instruction.LogicalShiftedRegister;pub const DataProcessing2Source = instruction.DataProcessing2Source;pub const DataProcessing3Source = instruction.DataProcessing3Source;pub const ConditionalSelect = instruction.ConditionalSelect;pub const LoadStore = instruction.LoadStore;pub const LoadStoreRegImm = instruction.LoadStoreRegImm;pub const LoadStoreRegImmFP = instruction.LoadStoreRegImmFP;pub const LoadStorePair = instruction.LoadStorePair;pub const LoadStorePairFP = instruction.LoadStorePairFP;pub const Branch = instruction.Branch;pub const UnconditionalBranchImm = instruction.UnconditionalBranchImm;pub const ConditionalBranch = instruction.ConditionalBranch;pub const UnconditionalBranchReg = instruction.UnconditionalBranchReg;pub const FPDataProcessing = instruction.FPDataProcessing;pub const FP1Source = instruction.FP1Source;pub const FP2Source = instruction.FP2Source;pub const FPCompare = instruction.FPCompare;pub const FPConversion = instruction.FPConversion;pub const FPImmediate = instruction.FPImmediate;pub const FMovGeneral = instruction.FMovGeneral;pub const Condition = instruction.Condition;Source: lib/choir/src/backends/aarch64/root.zig:2
pub const encoding = @import("encoding/root.zig");Also reachable as
Complete caller list for backends.aarch64.encoding.UnconditionalBranchImm.b
13 direct callers.
lib.choir.src.backends.aarch64.encoding.instruction.test_disassemble:_core_instruction_subset[function] — test source atlib/choir/src/backends/aarch64/encoding/instruction.zig:1628in nearest public ownerlib.choir.src.backends.aarch64.encoding.instructionlib.choir.src.backends.aarch64.encoding.instruction.test_golden:_Unconditional_branch_immediate[function] — test source atlib/choir/src/backends/aarch64/encoding/instruction.zig:1778in nearest public ownerlib.choir.src.backends.aarch64.encoding.instructionlib.pluck.src.bif.transpiler.test_transpile_conditional_network_as_S-expression_conditionals[function] — test source atlib/pluck/src/bif/transpiler.zig:371in nearest public ownerlib.pluck.src.bif.transpilerlib.pluck.src.evaluator.test_factor_WeightDD_composes_multiple_factors[function] — test source atlib/pluck/src/evaluator.zig:3810in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_factor_WeightDD_respects_branch_guards[function] — test source atlib/pluck/src/evaluator.zig:3851in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_factor_defers_WeightDD_refinement_when_node_limit_is_small[function] — test source atlib/pluck/src/evaluator.zig:3734in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_factor_prunes_zero-weight_branch[function] — test source atlib/pluck/src/evaluator.zig:3775in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_factor_supports_guarded_weights[function] — test source atlib/pluck/src/evaluator.zig:3699in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_symbolic_weight_compiler_handles_boolean_chain[function] — test source atlib/pluck/src/evaluator.zig:3920in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_symbolic_weight_compiler_handles_nested_if/case[function] — test source atlib/pluck/src/evaluator.zig:3997in nearest public ownertiny.pluck.evaluatorlib.pluck.src.evaluator.test_thunk_cache_-_repro_program_level_regression_for_pluck-rs-0cb[function] — test source atlib/pluck/src/evaluator.zig:3636in nearest public ownertiny.pluck.evaluatorlib.termtex.src.render.test_render_modulo_paper_idioms[function] — test source atlib/termtex/src/render.zig:194in nearest public ownertiny.termtex.renderertools.smg.src.tree.scanner.witness.test.cpp.test_C++_scanner_matches_pinned_C_scanner_with_by-value_state[function] — test; no exact target attools/smg/src/tree/scanner/witness/test.zig:186in nearest public ownertools.smg.src.tree.scanner.witness.test
Audit
| Definitions | 119 |
|---|---|
| Public names | 247 |
| Members | 293 |
| Version | 26.7.0 |
| Revision | daab053ee433 |